library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div50 is
port(clk:in std_logic;clkout:out std_logic);
end entity div50;

architecture behav of div50 is
begin 
process(clk)
	variable divcnt:integer := 0;
	--variable N: integer:= 5000000;
	begin 
	if clk'event and clk = '1' then
		if divcnt = 5000000 - 1 then
			clkout <= '1';
			divcnt := 0;
		else
			divcnt := divcnt + 1;
			clkout <= '0';
		end if;
	end if;
	
	end process;
end architecture behav;




